1. Field of the Invention
The invention relates to an integrated circuit chip and a method for fabricating the same, more particularly to an integrated circuit chip and a method for fabricating the same that can reduce production costs and that can increase production capacity.
2. Description of the Related Art
Referring to FIGS. 1A to 1C, a conventional method for fabricating an integrated circuit chip is shown. As shown in FIG. 1A, a die 10 having an upper surface provided with a plurality of solder pads 100 is attached to a tie bar 130 on a lead frame 13 by means of a double-side adhesive tape 12 to fix the die 10 on the lead frame 13. The solder pads 100 are exposed via a bore 1300 formed in the tie bar 130, as shown in FIG. 1D. Referring to FIG. 1B, each of the solder pads 100 is connected electrically to a respective lead 131 of the lead frame 13 via known wire bonding techniques by means of a conductive wire 14 that extends through the bore 1300. Referring to FIG. 1C, a plastic protective layer 15 is used to encapsulate the die 10 and a portion of the lead frame 13 to form an integrated circuit chip.
The following are some of the drawbacks of the conventional method for fabricating an integrated circuit chip:
1. The aforesaid method needs different kinds of lead frames for different kinds of packaging, such as TSOP, SOJ, QFP, SOP and so on. Thus, at least one mold is prepared for each customer, thereby increasing costs.
2. In the aforesaid method, double-side adhesive tape is needed to secure the die on the tie bar, thereby increasing the fabricating costs.
3. In the aforesaid method, it will take a long time to form the molds for the lead frames, thereby affecting the ability of manufacturers to compete.